The present invention relates generally to the fabrication of integrated circuits, and particularly to integrated circuits with an extremely high degree of compactness (e.g. ULSI devices) such as memories, logic arrays and, the like.
The formation of submicron-size contacts (to a semiconducting substrate and/or to conducting layers formed above the semiconducting substrate) represents a very critical aspect of a manufacturing process. Various technological problems must be solved to ensure continuity and uniformity of thickness of the resulting wiring.
Sputter deposition of aluminum alloys (such as aluminum-silicon or aluminum-copper) has been widely utilized in the past for filling contact holes and forming metallization layers. However, these techniques have proved inadequate for filling cavities having a submicron width, such as contact openings (holes) prearranged through an isolation dielectric layer, commonly of silicon oxide or a silicate glass.
Chemical vapor deposition ("CVD") is a technique of isotropically depositing metallic materials from a gas flow. This deposition technique ensures a very effective filling (step-coverage) of submicron cavities, and has rapidly found widespread application. The metal most commonly used for this purpose is tungsten.
Based on these developments, one contact fabrication technique comprises the following steps:
A) A barrier and adhesion layer (or multilayer) of titanium and/or titanium nitride is deposited, with a total thickness which is commonly between 50 and 200 nm. This deposition coats the surface of the semiconductor at the bottom of the openings formed through a layer of dielectric material, as well as the walls of the contact hole through the dielectric layer and the surface of the dielectric layer. At the bottom of the contact hole, the titanium and/or titanium nitride layer prevents an excessive diffusion of the subsequently deposited filler metal into the semiconducting substrate, and at the same time favors the establishment of a good electrical continuity (low contact resistance) through the formation of an alloy with the silicon substrate at the metal semiconductor interface. PA0 B) Subsequently, a layer of tungsten is deposited by CVD to fill completely the contact holes. PA0 C) A blanket (global) etch with a high selectivity toward the under-lying titanium nitride adhesion layer eliminates the tungsten from the surface of the dielectric layer while leaving plugs of tungsten within the contact holes. PA0 D) Standard plasma monitoring techniques will readily indicate when the tungsten has been etched sufficiently to expose the titanium nitride adhesion layer. Thereafter, a continued selective overetch of the tungsten must necessarily be carried out, in order to eliminate tungsten residues from the surface. (Such residues are likely to be found where the surface is nonplanar, e.g. along the line of a "step" caused by the topography of underlying layers.)
The problem is that, because of the erosion of the tungsten which is exposed to the overetch phase, the height of the tungsten plugs in the contacts may be undesirably reduced. If the height of plugs is excessively recessed in respect to the plane of the surface which covered by the adhesion layer of titanium nitride, cavities may occur during a subsequent sputter deposition of a metallization layer. For example, aluminum-silicon alloy, which is customarily deposited by sputtering, is susceptible to notching as illustrated in FIG. 1.
One modified approach might be to etch away the adhesion layer of titanium nitride from the surface of the dielectric, in order to reduce the degree of recession of the tungsten plugs in respect to the plane of the surface, before depositing a metallization layer of an aluminum-silicon alloy. Although this would reduce the tendency of the metallization layer to form occluded or not occluded (hidden or open) voids over recessed tungsten plugs, this approach would also cause a weakening in terms of long term reliability of the devices, especially because of electromigration phenomena of the Al/Si alloy.